Our paper titled "Bit-Sparsity Aware Acceleration with Compact CSD Code on Generic Matrix Multiplication" is accepted by the IEEE Transactions on Computers (TC). The ever-increasing demand for matrix multiplication in artificial intelligence (AI) and generic computing emphasizes the necessity of efficient computing power accommodating both floating-point and quantized integer. While state-of-the-art bit-sparsity-aware acceleration techniques have demonstrated impressive performance and efficiency in neural networks through software-driven methods such as pruning and quantization, these approaches are not always feasible in typical generic computing scenarios. In this paper, we propose Bit-Cigma, a hardware-centric architecture that leverages bit-sparsity to accelerate generic matrix multiplication. Experimental results confirm that Big-Cigma achieves high performance, area efficiency, and energy efficiency.

IEEE TC is widely considered as a prestigious journal in the domain of computer science and engineering. This works was mainly conducted in Professor Yongxin Zhu's lab at Shanghai Advanced Research Institute (SARI), Chinese Academy of Sciences (CAS). Mr Zixuan Zhu of SARI is the first author. Mr Xiaolong Zhou of the University of Electronic Science and Technology of China (UESTC), Chundong, Professor Li Tian of SARI, and Professor Yongxin Zhu are co-authors of this paper.